ASIC Verification Engineering Manager
Lead ASIC verification team to deliver block/full-chip verification, DV strategy, and first-pass silicon success.
Remote • United States
- Full Time
- Min. 15 YOE
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Lead ASIC verification team to deliver block/full-chip verification, DV strategy, and first-pass silicon success.
Prospect and develop key FSI end customers, drive HPC/AI-based sales and maintain a strategic pipeline to meet quota.
Design and optimize ASICs with Verilog/SystemVerilog, pre/post-silicon work and Ethernet protocol implementation.
Develop software validation plans, design and execute test cases, and implement automated tests for Ethernet-based HPC networking software.
Design and document HPC/AI solutions, selling technical architectures and driving revenue growth across customers and partners.
Lead ASIC design automation workflows and AI-driven optimization across multi-site EDA environments to improve throughput and scale.
Senior ASIC Design Engineer responsible for RTL design and timing closure in high-speed data paths for AI interconnect solutions.
Own design and development of middleware for storage applications, focusing on performance, scalability, and production readiness.
Lead cross-functional teams to drive delivery of high-performance, scalable networking solutions on time and within budget.
Develop software features for Linux device drivers and networking, profiling and optimizing for HPC/AI fabric.
Leads HPC networking product strategy, roadmap, and execution to deliver AI/ HPC scale-out solutions.
Perform SI simulation and analysis for high-speed interfaces, collaborating across teams to move products to production.
Architect and implement Kubernetes integration and fabric management for HPC/AI, building operators and cloud-native tooling.
Participate in development of UVM environments to verify RTL at block, unit, and SoC levels.
Lead accounting operations, financial reporting, and internal controls during growth with hands-on leadership.
Drive product messaging, positioning, and sales enablement assets for AI & HPC networking solutions across data center ecosystems.
Lead kernel software engineering team delivering Linux kernel components and upstreamed patches.
Develop system/board architectures and designs for next-generation Cornelis Networks fabric platforms.
Design and implement performance-critical features for CCL enablement on Cornelis Networks’ fabrics.
Senior ASIC Verification Engineer role focusing on UVM-based verification of RTL blocks and SoCs for high-performance AI/HPC networking.
Design and implement SAI object types and APIs; develop and maintain switch SDK components and test infrastructure.
Lead PCIe IP integration and silicon bring-up for high-performance ASICs with PCIe Gen4/Gen5/Gen6 expertise.
Develop and maintain fabric management software for topology, routing, and control planes in AI-first HPC environments.
Lead NOS platform porting, BSP development, and hardware integration for switch ASIC platforms with AI-first tooling and cross-NOS support.