Browse the full live job inventory for Axelera AI. This page is focused on current openings, while the overview tab highlights role groups and hiring patterns.
Lead safety architecture for AI-enabled SoCs, defining ISO 26262-compliant hardware safety and collaborating with partners and customers.
Remote • Munich, GermanyOwn end-to-end hardware quality management across IQC/OQC, supplier quality, NPI, and field returns with robust QMS.
Senior/Staff Backend Compiler Engineer role focusing on inhouse DSL features, compiler backend optimizations, and mapping workloads onto heterogeneous hardware.
Senior/Staff DFT engineer to design, implement and validate test solutions for multicore in-memory compute SoCs across Europe.
Electrical Engineer to join R&D Product Engineering team in Zurich focusing on embedded systems, power management, and hardware-software integration.
On-site • Zürich, SwitzerlandOwn AP, treasury and intercompany processes, automate workflows, and build ERP dashboards for multi-entity, multi-currency accounting.
Hybrid • Eindhoven, NetherlandsLeads automotive strategy, ecosystem development, and cross-functional initiatives to accelerate AI in automotive sector.
Identify, engage, and qualify potential customers in the EMEA region to create a steady pipeline for AEs.
Develop and execute verification plans for processor units with constrained random testbenches and cross-team collaboration to ensure coverage.
Remote • United KingdomLead UK sales strategy and regional expansion for Edge AI solutions across industrial OEMs and enterprise customers.
Remote • United KingdomDesign and implement RTL-based micro-architectures for in-house AI silicon, ensuring PPA targets.
Owns the product engineering lifecycle from tapeout to production and leads the Bristol validation lab.
Hybrid • Bristol, UKDesign, implement, and optimize MLIR-based frontend and graph-level compiler components to enable efficient AI workloads on heterogeneous hardware.
Leads silicon logical design, RTL implementation, and tape-out execution for complex AI accelerator SoCs with hands-on leadership.
Physical Design Engineer contributing to ASIC flow from RTL to GDS across synthesis, place and route, timing analysis, and physical verification.
On-site • Eindhoven, NetherlandsLead international logistics operations, optimize freight, customs, warehousing, and cross-border workflows across Asia-Europe-US.
Hybrid • Eindhoven, NetherlandsDevelop customer-facing SDK tools and pipelines for AI deployments, optimizing performance across heterogeneous hardware.
Remote • United KingdomLeads fabless operations, supply chain, quality, and delivery to scale AI hardware from prototypes to volume production.
Remote • United KingdomOwn PCIe and LPDDR validation end-to-end, including signal integrity, electrical compliance, protocol testing, and formal certification.
Hybrid • Bristol, UKSenior/Staff Silicon Physical Design Engineer responsible for RTL-to-GDS physical design including synthesis, floorplanning, place-and-route, timing, CTS, IP integration, and EDA tool usage.
Register interest to opportunities with Axelera AI following Polymesse event in Zurich.
On-site • Zürich, SwitzerlandDesign and optimize hardware architecture for AI accelerators, focusing on memory, inter-/intra-chip networks, and system integration.
Senior AI Research Engineer developing and optimizing multimodal AI models for real-time, high-efficiency inference across edge, server, and embodied AI environments.
Drive multi-year RTL/system-level hardware direction for AI accelerator SoCs with cross-functional leadership.